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PRELIMINARY TECHNICAL DATA
a
Preliminary Data Sheet
FEATURES AD7788 Has 16-Bit Resolution AD7789 Has 24-Bit Resolution POWER Specified for Single 3 V and 5 V Operation Normal: 65 A typical Power-Down: 1 A RMS Noise: 1.5 V AD7788: 16-Bit p-p Resolution AD7789: 19-Bit p-p Resolution (21.5 Bits Effective Resolution) Simultaneous 50 Hz and 60 Hz Rejection Internal Clock Oscillator VDD Monitor Channel 10-Lead SOIC Package INTERFACE 3-Wire Serial SPITM, QSPITM, MICROWIRETM and DSP-Compatible Schmitt Trigger on SCLK APPLICATIONS SMART Transmitters Battery Applications
Low Power, 16/24-Bit Sigma-Delta ADC AD7788/AD7789
Portable Instrumentation Sensor Measurement Temperature Measurement Pressure Measurements Weigh Scales 4 to 20 mA Loops GENERAL DESCRIPTION
The AD7788/AD7789 are low-power, complete analog front ends for low frequency measurement applications. The AD7789 contains a 24-bit - ADC with one differential input. The AD7788 is a 16-bit version of the AD7789. The device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device. The output data rate is 16.6 Hz which gives simultaneous 50 Hz/ 60 Hz rejection. The part operates from a single 3 V or 5 V supply. When operating from a 3 V supply, the power dissipation for the part is 195 W typical. The AD7788/AD7789 is housed in a 10-lead SOIC package.
FUNCTIONAL BLOCK DIAGRAM
REFIN(+) REFIN(-)
GND 32 kHz CLOCK
VDD
AD7788 / AD7789
AIN(+) AIN(-) Sigma Delta ADC* *AD7788: 16-BIT ADC *AD7789: 24-BIT ADC
SERIAL INTERFACE AND CONTROL LOGIC
DOUT/RDY DIN SCLK CS
SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
REV. PrA 12/02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD7789-SPECIFICATIONS1
Parameter ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes 2 Resolution Output Noise Integral Nonlinearity 2 Offset Error Offset Error Drift vs. Temperature Full-Scale Error 3 Gain Drift vs. Temperature Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Analog Input Current Average Input Current Average Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz2 REFERENCE INPUT REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz AD7789B 16.6 24 19 1.5 +15 +3 +10 +10 +0.5 80
(VDD = +2.7 V to +3.6 V or +4.75 V to +5.25 V; REFIN (+) = +2.5 V; REFIN(-) = GND; GND = 0 V, all specifications TMIN to TMAX unless otherwise noted)
Units Hz nom Bits min Bits p-p V RMS typ ppm of FSR Max V typ nV/OC typ V typ ppm/OC typ dB min 100 dB typ, AIN = 1 V V nom V min V max nA/V typ pA/V/OC typ dB min dB min dB min V nom V min V max V min V max A/V typ nA/V/OC typ dB min dB typ dB typ 50 + 1 Hz, 60 + 1 Hz AIN = 1 V 100 dB typ 50 + 1 Hz, 60 + 1 Hz REFIN = REFIN(+) - REFIN(-) REFIN = REFIN(+) - REFIN(-) Test Conditions/Comments
+REFIN GND - 30 mV VDD + 30 mV +350 +2 70 90 100 2.5 1 V DD GND - 30 mV VDD + 30 mV 0.5 +0.01 70 110 110
Input current varies with Input Voltage
50 + 1 Hz, 60 + 1 Hz AIN = 1 V 50 + 1 Hz, 60 + 1 Hz
NOTES 1 Temperature Range -40 o C to +85 o C. 2 Guaranteed by design and/or characterization data on production release. 3 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions. Specifications subject to change without notice.
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REV. PrA 12/02
to +3.6 V or REFIN (+) = +2.5 AD7788-SPECIFICATIONS1 (VDD == 0+2.7allV specifications+4.75toV Tto +5.25 V;otherwise noted) V; REFIN(-) = GND; GND V, T unless
t
MIN MAX
PRELIMINARY TECHNICAL DATA
AD7788B 16.6 16 16 1.5 +15 +3 +10 +10 +0.5 80 +REFIN/GAIN GND - 30 mV VDD + 30 mV +350 +2 70 90 100 2.5 1 VDD GND - 30 mV VDD + 30 mV 0.5 +0.01 70 110 110 Units Hz nom
Parameter ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes 2 Resolution Output Noise Integral Nonlinearity 2 Offset Error Offset Error Drift vs. Temperature Full-Scale Error 3 Gain Drift vs. Temperature Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Analog Input Current Average Input Current Average Input Current Drift Normal Mode Rejection 2 @ 50 Hz, 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz2 REFERENCE INPUT REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits 2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz
Test Conditions/Comments
Bits min Bits p-p V RMS typ ppm of FSR Max V typ nV/OC typ V typ ppm/OC typ dB min 100 dB typ V nom V min V max nA/V typ pA/V/OC typ dB min dB min dB min V nom V min V max V min V max A/V typ nA/V/OC typ dB min dB typ dB typ 50 + 1 Hz, 60 + 1 Hz AIN = 1 V 100 dB typ 50 + 1 Hz, 60 + 1 Hz REFIN = REFIN(+) - REFIN(-) REFIN = REFIN(+) - REFIN(-)
Input current varies with Input Voltage
50 + 1 Hz, 60 + 1 Hz AIN = 1 V 50 + 1 Hz, 60 + 1 Hz
NOTES 1 Temperature Range -40 oC to +85 o C. 2 Guaranteed by design and/or characterization data on production release. 3 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions. Specifications subject to change without notice.
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REV. PrA 12/02
PRELIMINARY TECHNICAL DATA
AD7788/AD7789-SPECIFICATIONS1
Parameter LOGIC INPUTS All Inputs Except SCLK2 VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt-Triggered Input) 2 VT(+) VT(-) VT(+) - VT(-) VT(+) VT(-) VT(+) - VT(-) Input Currents Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding CLOCK OSCILLATOR Clock Frequency Start-Up Time (at Power-On) POWER REQUIREMENTS3 Power Supply Voltage VDD - GND Power Supply Currents I DD Current IDD (power-down mode) AD7788B/ AD7789B Units Test Conditions/Comments 0.8 0.4 2.0 1.4/2 0.8/1.4 0.3/0.85 0.95/2 0.4/1.1 0.3/0.85 +1 TBD 10 VDD - 0.6 0.4 4 0.4 +1 10 Offset Binary 32.768 + 2% 0.5 1 V max V max V min V min/V V min/V V min/V V min/V V min/V V min/V A max A max pF typ V min V max V min V max A max pF typ max max max max max max VDD = 5 V VDD = 3 V VDD = 3 V or 5 V VDD = 5 V VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VDD = 3 VIN = VDD VIN = GND All Digital Inputs VDD VDD VDD VDD = = = = 3 3 5 5 V, ISOURCE = 100 A V, ISINK = 100 A V, ISOURCE = 200 A V, ISINK = 1.6 mA
kHz min/max ms typ ms max
2.7/3.6 4.75/5.25 65 75 90 1
V min/max V min/max A A A A typ typ max typ
VDD = 3 V nom VDD = 5 V nom 3 V Power Supply 5 V Power Supply
NOTES 1 Temperature Range -40 oC to +85 o C. 2 Guaranteed by design and/or characterization data on production release. 3 Digital inputs equal to V DD or GND. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD7788/AD7789 TIMING CHARACTERISTICS1, 2
Parameter t1 t4 t5 Read Operation t2 t34 t65,
6
(VDD = +2.7 V to +3.6 V or +4.75 V to +5.25 V; GND = 0 V, REFIN(+) = +2.5 V, REFIN(-) = GND, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted)
Units s nom ns min ns min ns ns ns ns ns ns ns ns ns ns ns ns ns ns min max max min max max min max max min min min min min Conditions/Comments Internal Clock Period SCLK High Pulsewidth SCLK Low Pulsewidth CS Falling Edge to DOUT/RDY Active Time VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V SCLK Active Edge to Data Valid Delay3 VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V Bus Relinquish Time after CS Inactive Edge SCLK Inactive Edge to CS Inactive Edge SCLK Inactive Edge to DOUT/RDY High CS Falling Edge to SCLK Active Edge Setup Time3 Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time CS Rising Edge to SCLK Edge Hold Time
Limit at TMIN, TMAX (B Version) 30.5175 100 100 0 60 80 0 60 80 10 80 100 10 0 30 25 0
t7 t8 Write Operation t9 t 10 t 11 t 12
NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figures 2 and 3. 3 SCLK active edge is falling edge of SCLK. 4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or V OH limits. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
ISINK (1.6 mA with VDD = 5 V, 100 A with VDD = 3 V)
TO OUTPUT PIN 50 pF
+1.6 V
ISOURCE (200 A with VDD = 5 V, 100 A with VDD = 3 V)
Figure 1. Load Circuit for Timing Characterization
CS(I)
CS (I)
t2
DOUT/RDY(O) MSB MSB LSBLSB
t8
t7
SCLK (I)
t10
t13
t4 t5
t9
t11 t 12
DIN (I) MSB MSB LSB LSB
SCLK(I)
t6
I = Input, O = Output
I = Input, O = Output
Figure 2. Read Cycle Timing Diagram
Figure 3. Write Cycle Timing Diagram
REV. PrA 12/02
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PRELIMINARY TECHNICAL DATA
AD7788/AD7789
ABSOLUTE MAXIMUM RATINGS* (TA = +25C unless otherwise noted) PIN CONFIGURATION
VDD to GND......................................... -0.3 V to +7 V Analog Input Voltage to GND.......-0.3 V to VDD + 0.3 V Reference Input Voltage to GND...-0.3 V to VDD + 0.3 V Total AIN/REFIN Current (Indefinite)................30 mA Digital Input Voltage to GND.......-0.3 V to VDD + 0.3 V Digital Output Voltage to GND.....-0.3 V to VDD + 0.3 V Operating Temperature Range...............-40C to +85C Storage Temperature Range.................-65C to +150C Maximum Junction Temperature........................+150C SOIC Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 206C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . 44C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . 300C IR Reflow, Peak Temperature . . . . . . . . . . . . . . . 220C
NOTES * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SCLK 1 CS
2
10
DIN DOUT/RDY VDD GND REF(-)
AD7788 /AD7789
TOP VIEW (Not To Scale)
9 8 7 6
AIN(+) 3 AIN(-) 4 REF(+) 5
ORDERING GUIDE
Model AD7788BRM AD7789BRM
Temperature Range -40C to +85C -40C to +85C
Package Description 10-Lead Micro Small Outline IC 10-Lead Micro Small Outline IC
Package Option RM-10 RM-10
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7788/AD7789 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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REV. PrA 12/02
PRELIMINARY TECHNICAL DATA AD7788/AD7789
PIN FUNCTION DESCRIPTIONS
Pin No. 7 1
Mnemonic GND SCLK
Function Ground Reference Point. Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a schmitt triggered input making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low allowing the ADC to operate in 3-wire mode with SCLK, DIN and DOUT used to interface with the device. Analog Input. AIN(+) is the positive terminal of the fully-differential analog input. Analog Input. AIN(-) is the negative terminal of the fully-differential analog input. Positive Reference Input. REFIN(+) can lie anywhere between VDD and GND + 1 V. The nominal reference voltage (REFIN(+) - REFIN(-)) is 2.5 V, but the part functions with a reference from 1 V to VDD. Negative Reference Input. This reference input can lie anywhere between GND and VDD - 1 V. Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose in this interface. When CS is low, it functions as a Serial Data Output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin when CS is low, going low to indicate the completion of a conversion. If the data is not read after the conversion, the data ready pin will go high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor indicating that valid data is available. Using an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information in placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. The end of a conversion is also indicated by the RDY bit in the Status register. When CS is high, the DOUT/RDY pin is tri-stated but the RDY bit remains active. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC, the register selection bits of the Communications register identifying the appropriate register. Supply Voltage, 3 V or 5 V Nominal.
2
CS
3 4 5
AIN(+) AIN(-) REFIN(+)
6 9
REFIN(-) DOUT/RDY
10
DIN
8
V DD
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers which are described in the following pages. the following descriptions, Set implies a Logic 1 state and Cleared implies a Logic 0 state, unless otherwise stated. Communications Register (RS1, RS0 = 0, 0)
In
The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications Register. This is the default state of the interface and, on power-up or after a RESET, the ADC is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 1 outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. REV. PrA 12/02 -7-
PRELIMINARY TECHNICAL DATA
AD7788/AD7789
CR7 WEN ( 0 ) CR6 0(0) CR5 RS1(0) CR4 RS0(0) CR3 R/W(0) CR2 CREAD(0) CR1 CH1(0) CR0 CH0(0)
Table 1.
Communications Register Bit Designations
Bit Location CR7
Bit Name WEN
Description Write Enable Bit. A 0 must be written to this bit so that the write to the Communications Register actually occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communications Register. This bit must be programmed with a logic 0 for correct operation. Register Address Bits. These address bits are used to select which of the ADC's registers are being selected during this serial interface communication. See Table 2. A zero in this bit location indicates that the next operation will be a write to a specified register. A one in this position indicates that the next operation will be a read from the designated register. Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read i.e. the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The Communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 001111XX must be written to the communications register. To exit the continuous read mode, the instruction 001110XX must be written to the communications register while the RDY pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in the continuous read mode until an instruction is to be written to the device.
CR6 CR5-CR4 CR3
0 RS1-RS0 R/ W
CR2
CREAD
CR1-CR0
CH1-CH0 These bits are used to select the analog input channel. The differential channel can be selected (AIN(+)/AIN(-)) or an internal short (AIN(-)/AIN()) can be selected. Alternatively, the power supply can be selected i.e. the ADC can measure the voltage on the power supply which is useful to monitor power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for conversion. The ADC uses a 1.2V + 5% on-chip reference as the reference source for the analog to digital conversion. Any change in channel resets the filter and a new conversion is started.
Table 2. Register Selection Table
RS1 0 0 0 1 1
RS0 0 0 1 0 1
Register Communications Register during a Write Operation Status Register during a Read Operation Mode Register Reserved Data Register
Register Size 8-Bit 8-Bit 8-Bit 8-Bit 16-Bit (AD7788) 24-Bit (AD7789)
Table 3.
Channel Selection Table
CH1 0 0 1 1
CH0 0 1 0 1
Channel AIN(+) - AIN(-) Reserved AIN(-) - AIN(-) VDD Monitor -8- REV. PrA 12/02
PRELIMINARY TECHNICAL DATA AD7788/AD7789
Status Register (RS1, RS0 = 0, 0; Power-on Reset = 00h) The Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communications Register selecting the next operation to be a read and load bit RS2, RS1 and RS0 with 0, 0, 0. Table 4 outlines the bit designations for the Status Register. SR0 through SR7 indicate the bit loctions, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/ reset default status of that bit. SR7 RDY ( 1 ) Table 4. Bit Location SR7 RDY Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in powerdown mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones. Error sources include Overrange, Underrange. Cleared by a write operation to start a conversion. This bit is automatically cleared. This bit is automatically cleared. This bit is automatically set. This bit is automatically cleared if the device is an AD7788 and it is automically set if the device is an AD7789. This bit can be used to distinguish between the AD7788 and AD7789. Bit Name SR6 ERR(0) SR5 0(0) SR4 0(0) SR3 1(1) SR2 WL(1/0) SR1 CH1(0) SR0 CH0(0)
Status Register Bit Designations
Description
SR6
ERR
SR5 SR4 SR3 SR2 SR1-SR0
0 0 1 1/0
CH1-CH0 These bits indicate which channel is being converted by the ADC.
Mode Register (RS1, RS0 = 0, 1; Power-on Reset = 00h) The Mode Register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode or place the device is powerdown mode. Table 5 outlines the bit designations for the Mode register. MR0 through MR7 indicate the bit loctions, MR denoting the bits are in the Mode Register. MR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit. MR7 MD1(0) Table 5. MR6 MD0(0) MR5 0(0) MR4 0(0) MR3 0(0) MR2 U/B (0) MR1 1(1) MR0 0(0)
Mode Register Bit Designations
REV. PrA 12/02
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PRELIMINARY TECHNICAL DATA
AD7788/AD7789
Bit Location Bit Name Description MR7-MR6 MD1- MD0 Mode Select Bits. These bits select between continuous conversion mode, single conversion mode and standby mode. In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied or, alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period 2/ fadc while subsequent conversions are available at a frequency of fadc. In single conversion mode, the ADC is placed in powerdown mode when conversions are not being performed. When single conversion mode is selected, the ADC powers up and performs a single conversion which occurs after a period 2/fadc. The conversion result in placed in the data register, RDY goes low and the ADC returns to powerdown mode. The conversion remains in the DATA register and RDY remains active (low) until another conversion is performed. See Table 6. MR5-MR3 0 MR2 U/B These bits must be programmed with a logic 0 for correct operation. Unipolar/Bipolar bit. Set by user to enable unipolar coding i.e. zero differential input will result in 0000 hex output and a full-scale differential input will result in FFFF hex output. Cleared by the user to enable bipolar coding. Negative full-scale differential input will result in an output code of 0000 hex, zero differential input will result in an output code of 8000 hex and a positive full-scale differential input will result in an output code of FFFF hex. This bit must be programmed with a logic 1 for correct operation. This bit must be programmed with a logic 0 for correct operation. MD1 0 0 1 1 MD0 0 1 0 1 Table 6. Mode Continuous Conversion Mode (Default) Reserved Single Conversion Mode Powerdown Mode Operating Modes
MR1 MR0
1 0
Data Register (RS1, RS0 = 1, 1; Power-on Reset = 0000h (AD7788) and 000000h (AD7789)) The conversion result from the ADC is stored in this data register. This is a read only register. On completion of a read operation from this register, the RDY bit/pin is set.
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REV. PrA 12/02

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